1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology and, more particularly, to a semiconductor device having a monitoring function and a method for driving the same.
2. Description of the Related Art
FIG. 1 is a block diagram illustrating a conventional semiconductor device 100.
Referring to FIG. 1, the semiconductor device 100 includes an internal signal processing block 110, a command decoding block 120, a memory block 130, an output block 140, a fuse block 150, and an internal voltage generation block 160.
The internal signal processing block 110 generates internal signals CID[1:0], ICKE, ICSB, ICMDs, and IADD[#:0] that correspond to external signals C[1:0], CKE, CSB, CMDs, ADD[#:0], CLK, and CLKB transferred from an external device (not illustrated). The command decoding block 120 decodes some ICK, ICSB, and ICMDs of the internal signals generated from the internal signal processing block 110. The memory block 130 performs a write operation and a read operation in response to some IADD[#:0], etc of the internal signals generated from the internal signal processing block 110 and some internal control signals ACT, PRE, RD, WT, etc decoded from the command decoding block 120. The output block 140 provides read data NOMAL_DATA[63:0] read from the memory block 130 to the external device through first to eighth data pads DQ0 to DQ7 in response to a data width option signal X8.
The internal signal processing block 110 includes circuits for processing the external signals C[1:0], CKE, CSB, CMDs, ADD[#:0], CLK, and CLKB according to internal characteristics. The external signals C[1:0], CKE, CSB, CMDs, ADD[#:0], CLK, and CLKB include chip identification signals C[1:0], a clock enable signal CKE, command signals CMDs, address signals ADD[#:0], and differential clock signals CLK and CLKB, wherein the external signals C[1:0], CKE, CSB, CMDs, ADD[#:0], CLK, and CLKB will be named as the signals for this description.
For example, the internal signal processing block 110 includes input units RxS, a clock transfer unit, delay units tIS/tIH, and synchronization units F/F. The input units RxS buffer the chip identification signals C[1:0], the clock enable signal CKE, the command signals CMDs, the address signals ADD[#:0], and the differential clock signals CLK and CLKB. The clock transfer unit transfers an internal clock signal CLK′, which is outputted from any one of the input units RxS, to a predetermined path. The delay units tIS/tIH adjust the setup and hold times of internal chip identification signals C′[1:0], an internal clock enable signal CKE′, internal command signals CMDs′, and internal address signals ADD′[#:0] which are outputted from the other input units RxS. The synchronization units F/F synchronize signals outputted from the delay units tIS/tIH with a clock signal outputted from the clock transfer unit.
The command decoding block 120 combines some ICKE, ICSB, and ICMDs of the signals outputted from the internal signal processing block 110, and generates internal control signals SREF, REF, PDEN, ACT, PRE, RD, WT, MRS, ZQC, etc.
The memory block 130 outputs stored write data as the read data NOMAL_DATA[63:0] in a read operation. Particularly, the memory block 130 decides the amount of data to be outputted at a time according to a data width option mode. For example, the memory block 130 simultaneously outputs read data NOMAL_DATA[31:0] and NOMAL_DATA[63:32] of first and second groups in an X8 mode, and simultaneously outputs the read data NOMAL_DATA[31:0] of the first group between the read data NOMAL_DATA[31:0] and NOMAL_DATA[63:32] of the first and second groups in an X4 mode.
The output block 140 outputs some or all of the read data NOMAL_DATA[63:0] to the first to eighth data pads DQ0 to DQ7 according to a data width option signal X8 in the read operation. For example, the output block 140 includes a first output driving unit 141 that outputs the read data NOMAL_DATA[31:0] of the first group to the first to fourth data pads DQ0 to DQ3 regardless of the data width option signal X8 in the read operation, and a second output driving unit 143 that outputs the read data NOMAL_DATA[63:32] of the second group to the fifth to eighth data pads DQ4 to DQ7 according to the data width option signal X8 in the read operation.
The fuse block 150 is used for repairing the memory block 130. The internal voltage generation block 160 generates internal voltages used for the operations of the memory block 130, the fuse block 150, etc.
FIG. 2 is a timing diagram for describing an operation of the semiconductor device 100 shown in FIG. 1.
Referring to FIG. 2, the semiconductor device 100 performs an initialization operation for an initialization period R after a power-up period, and performs a boot-up operation for a boot-up period B after the initialization period R. For example, the semiconductor device 100 initializes the logic values of logic circuits, requiring an initialization operation for the initialization period R, to a default value, loads fuse signals programmed in the fuse block 150 for the boot-up period B, and generates an internal voltage through the internal voltage generation block 160.
The power-up period includes a period in which a power supply voltage VDD is ramped to a target level, the initialization period R includes a period in which a reset signal RESET_n inputted from an external device is activated to a logic low level, and the boot-up period B includes a period from the time point at which the reset signal RESET_n is deactivated to a logic high level to the time point at which the clock enable signal CKE is activated to a logic high level.
Then, the semiconductor device 100 performs a predetermined operation for a normal period after the boot-up period Bin response to the command signals CMDs and the address signals ADD[#:0]. For example, the semiconductor device 100 outputs the first to 32th read data NOMAL_DATA[31:0] through the first to fourth data pads DQ0 to DQ3, except for the fifth to eighth data pads DQ4 to DQ7, for the normal period. This describes the case in which the data width option of the semiconductor device 100 is set as the X4 mode, that is, the case in which the first output driving unit 141 is enabled and the second output driving unit 143 is disabled. Of course, when the data width option is set as the X8 mode, all the first and second driving units 141 and 143 are enabled to output the first to 64th read data NOMAL_DATA[63:0] through the first to eighth data pads DQ0 to DQ7.
The semiconductor device 100 may be controlled to perform a predetermined operation at a predetermined timing.
However, the semiconductor device 100 has the following concerns.
The semiconductor device 100 may receive the command signals CMDs only after the dock enable signal CKE is activated to a logic high level. This is because the differential clock signals CLK and CLKB may be inputted after the time point at which the clock enable signal CKE is activated to the logic high level.
Meanwhile, the semiconductor device 100 performs the initialization operation or the boot-up operation when the clock enable signal CKE is in an undefined state or a deactivated state. In the initialization period R, the clock enable signal CKE is in the undefined state, and in the boot-up period B, the clock enable signal CKE is in the deactivated state.
When the semiconductor device 100 performs the initialization operation or the boot-up operation, it is not easy to analyze failures caused by the initialization operation or the boot-up operation. This is because the command signals CMDs may not be inputted for the initialization period R and the boot-up period B.
That is, in the semiconductor device 100, since the input of the command signals CMDs is not allowed for the initialization period R and the boot-up period B, internal signals related to the initialization operation and the boot-up operation may not be monitored.